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lt c4367 1 4367fa for more information www.linear.com/ltc4367 typical application features description 100v overvoltage , undervoltage and reverse supply protection controller 24v automotive application with +100v, C40v protection applications n wide operating voltage range: 2.5v to 60v n overvoltage protection to 100v n reverse supply protection to C40v n ltc4367: blocks 50hz and 60hz ac power n ltc4367: 32ms recovery from fault n ltc4367-1: fast 500s recovery from fault n no input capacitor or tvs required for most applications n adjustable undervoltage and overvoltage thresholds n controls back-to-back n-channel mosfets n low operating current: 70a n low shutdown current: 5a n 8-pin msop and 3mm 3mm dfn packages n portable instrumentation n industrial automation n laptops n automotive surge (load dump) protection l , lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. load protected from reverse and overvoltage at v in the lt c ? 4367 protects applications where power sup - ply input voltages may be too high , too low or even negative. it does this by controlling the gate voltages of a pair of external n-channel mosfets to ensure that the output stays within a safe operating range .the ltc4367 withstands voltages between ?40v and 100v and has an operating range of 2.5v to 60v, while consuming only 70a in normal operation. two comparator inputs allow configuration of the over - voltage ( ov) and undervoltage (uv) set points using an external resistive divider . a shutdown pin provides external control for enabling and disabling the mosfet s as well as placing the device in a low current shutdown state . a fault output indicates that the gate pin is pulling low when the part is in shutdown or the input voltage is outside the uv and ov set points. the ltc4367 has a 32ms turn-on delay that debounces live connections and blocks 50hz to 60hz ac power . for fast recovery after faults , the ltc4367 -1 has a reduced turn-on delay of 500s. v in uvov shdn ov = 36vuv = 7v 4367 ta01a v out fault gate v in 24v v out 2a si7942 gnd ltc4367 1500k121k 29.4k 464k downloaded from: http:/// +70v 20v/div 4367 ta01b gnd ?40v 20v/div 200ms/div ov = 36vuv = 7v out v out v in v in v valid window
lt c4367 2 4367fa for more information www.linear.com/ltc4367 absolute maximum ratings supply voltage v in ........................................................ ? 40v to 100v input voltages ( note 3 ) uv , shdn .............................................. ?0. 3v to 80v ov ............................................................ ?0. 3v to 5v v out ....................................................... ?0. 3v to 80v output voltages fa u lt ..................................................... ?0. 3v to 80v gate ( note 4 ) ......................................... ? 40v to 75v top view dd package 8-lead (3mm 3mm) plastic dfn 5 6 7 8 9 4 3 2 1 gatev out faultshdn v in uvov gnd exposed pad (pin 9) pcb ground connection optional t jmax = 150c, ja = 43c/w, jc = 5.5c/w 12 3 4 v in uvov gnd 87 6 5 gatev out faultshdn top view ms8 package 8-lead plastic msop t jmax = 150c, ja = 160c/w input currents shdn , uv ......................................................... ? 1ma ov ...................................................................... ? 1ma operating ambient temperature range lt c4367 c ................................................ 0c to 70c lt c4367 i ............................................. ? 40 c to 85c lt c4367 h .......................................... ? 40 c to 125c storage temperature range .................. ? 65 c to 150c lead temperature ( soldering , 10sec ) for msop only .................................................. 300 c (note 1, note 2) pin configuration downloaded from: http:///
lt c4367 3 4367fa for more information www.linear.com/ltc4367 lead free finish tape and reel part marking* package description temperature range ltc4367cdd#pbf ltc4367cdd#trpbf lgtf 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4367cdd-1#pbf ltc4367cdd-1#trpbf lgvw 8-lead (3mm 3mm) plastic dfn 0c to 70c ltc4367idd#pbf ltc4367idd#trpbf lgtf 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc4367idd-1#pbf ltc4367idd-1#trpbf lgvw 8-lead (3mm 3mm) plastic dfn ?40c to 85c ltc4367hdd#pbf ltc4367hdd#trpbf lgtf 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc4367hdd-1#pbf ltc4367hdd-1#trpbf lgvw 8-lead (3mm 3mm) plastic dfn ?40c to 125c ltc4367cms8#pbf ltc4367cms8#trpbf ltgtd 8-lead plastic msop 0c to 70c ltc4367cms8-1#pbf ltc4367cms8-1#trpbf ltgvx 8-lead plastic msop 0c to 70c ltc4367ims8#pbf ltc4367ims8#trpbf ltgtd 8-lead plastic msop ?40c to 85c ltc4367ims8-1#pbf ltc4367ims8-1#trpbf ltgvx 8-lead plastic msop ?40c to 85c ltc4367hms8#pbf ltc4367hms8#trpbf ltgtd 8-lead plastic msop ?40c to 125c ltc4367hms8-1#pbf ltc4367hms8-1#trpbf ltgvx 8-lead plastic msop ?40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. electrical characteristics symbol parameter conditions min typ max units v in , v out v in input voltage: operating range protection range l l 2.5 ?40 60 100 v v v in(uvlo) input supply undervoltage lockout v in rising l 1.8 2.2 2.4 v i vin input supply current: on off shdn = 2.5v shdn = 0v, v in = v out l l 30 5 90 20 a a i vin(r) reverse input supply current v in = ?40v, v out = 0v l ?1.5 ?2.5 ma i vout v out input current: on off reverse shdn = 2.5v, v in = v out shdn = 0v, v in = v out v in = ?40v, v out = 0v l l l 40 3 20 110 15 50 a a a gate ?v gate gate drive (gate ? v out ) v in = v out = 5.0v, i gate = 0a, ?1a v in = v out = 12v to 60v, i gate = 0a, ?1a l l 7.2 10 8.7 11 10.8 13.1 v v i gate(up) gate pull up current gate = 15v, v in = v out = 12v l ?20 ?35 ?60 a i gate ( slow ) gate slow pull down current gate = 20v , v in = v out = 12v l 50 90 160 a i gate(fast) gate fast pull down current gate = 20v , v in = v out = 12v l 30 60 90 ma t gate ( slow ) slow turn off delay c gate = 2. 2nf , shdn falling , v in = v out = 12v l 150 250 370 s t gate(fast) gate fast turn off delay c gate = 2.2nf, uv or ov fault l 2 4 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 2.5v to 60v, unless otherwise noted. (note 2) order information ( http:// www .linear.com/product/ltc4367#orderinfo ) downloaded from: http:///
lt c4367 4 4367fa for more information www.linear.com/ltc4367 symbol parameter conditions min typ max units t d(on) gate turn-on delay time v in = 12v , power good to ?v gate > 0v , c gate = 2. 2nf ltc4367 ltc4367-1 l l 22 0.2 32 0.5 45 1.2 ms ms uv, ov v uv uv input threshold voltage uv falling l 492.5 500 507.5 mv v ov ov input threshold voltage ov rising l 492.5 500 507.5 mv v uvhyst uv input hysteresis v in = v out = 12v l 20 25 32 mv v ovhyst ov input hysteresis v in = v out = 12v l 20 25 32 mv i leak uv, ov leakage current v = 0.5v, v in = 60v l 10 na t fault uv, ov fault propagation delay overdrive = 50mv v in = v out = 12v l 1 2 s shdnv shdn shdn input threshold shdn falling l 0.4 0.75 1.2 v i shdn shdn input current shdn = 10v, v in = 60v l 15 na t start delay coming out of shutdown mode shdn rising to fault released , v in = v out = 12v ltc4367 ltc4367-1 l 400 125 800 250 1200 500 s s t shdn(f) shdn to fault asserted v in = v out = 12v l 1.5 3 s t lowpwr delay from turn off to low power operation v in = v out = 12v ltc4367 ltc4367-1 l l 20 0.125 32 0.3 48 0.6 ms ms fault v ol fault output voltage low i fault = 500a, v in = 12v l 0.15 0.4 v i fault fault leakage current fault = 5v, v in = 60v l 200 na note 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3 . these pins have a diode to gnd. they may go below ?0.3v if the current magnitude is limited to less than 1ma.note 4. the gate pin is referenced to v out and does not exceed 73v for the entire operating range. electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 2.5v to 60v, unless otherwise noted. (note 2) downloaded from: http:///
lt c4367 5 4367fa for more information www.linear.com/ltc4367 typical performance characteristics v out operating current vs temperature v out shutdown current vs temperature v out current vs reverse v in v in operating current vs temperature v in shutdown current vs voltage v in supply current vs voltage (C40v to 100v) gate drive vs gate current gate drive vs v in supply voltage gate drive vs temperature v in = 12v v in = 2.5v v in = 60v shdn = 2.5v v in = v out temperature (c) ?50 ?25 0 25 50 75 100 125 0 10 20 30 40 50 i vin (a) 4367 g01 v in (v) 0 10 20 30 40 50 60 0 2 4 6 8 i vin (a) 4367 g02 t a = 125c t a = 70c t a = 25c t a = ?45c shdn = 0v v in = v out uv = shdn = 0v v out = 0v v in (v) ?50 ?25 0 25 50 75 100 ?2000 ?1500 ?1000 ?500 0 500 i vin (a) 4367 g03 t a = 125c t a = 25c t a = ?45c v out = 12v v out = 2.5v v out = 60v shdn = 2.5v v in = v out temperature (c) ?50 ?25 0 25 50 75 100 125 0 10 20 30 40 50 i vout (a) 4367 g04 v out = 12v v out = 2.5v v out = 60v temperature (c) ?50 ?25 0 25 50 75 100 125 0 1 2 3 4 5 6 i vout (a) 4367 g05 shdn = 0v v in = v out 25c 125c ?45c v out = 0v v in (v) 0 ?10 ?20 ?30 ?40 0 5 10 15 20 i vout (a) 4367 g06 v in = v out v out = 0v t a = 25c i gate = ?1a v in (v) 0 10 20 30 40 50 60 0 4 8 12 16 ?v gate (v) 4367 g07 v in = v out = 12v v in = v out = 2.5v v in = v out = 60v i gate = 1a temperature (c) ?50 ?25 0 25 50 75 100 125 0 3 6 9 12 15 ?v gate (v) 4367 g08 v in = v out = 12v i gate(up) (a) 0 ?10 ?20 ?30 ?40 ?50 ?60 0 2 4 6 8 10 12 ?v gate (v) 4367 g09 t a = 125c t a = 25c t a = ?45c downloaded from: http:///
lt c4367 6 4367fa for more information www.linear.com/ltc4367 uv/ov propagation delay vs overdrive ltc4367 gate turn-on delay time vs temperature ltc4367 gate turn-on delay time vs v in ov threshold vs temperature uv/ov/ shdn leakage vs temperature uv threshold vs temperature typical performance characteristics v in = v out = 12v temperature (c) ?50 ?25 0 25 50 75 100 125 492 496 500 504 508 v uv (mv) 4367 g10 v in = v out = 12v temperature (c) ?50 ?25 0 25 50 75 100 125 492 496 500 504 508 v ov (mv) 4367 g11 v in = v out = 60v temperature (c) ?50 ?25 0 25 50 75 100 125 ?2 0 2 4 6 8 i leak (na) 4367 g12 shdn = 60v uv/ov = 0.5v v in = v out = 12v t a = 25c overdrive (mv) 1 10 100 1k 0 10 20 30 40 50 t fault (s) 4367 g13 temperature recovery delay time vs v in = 12v, 60v v in = 2.5v temperature (c) ?50 ?25 0 25 50 75 100 125 0 10 20 30 40 50 4367 g14 t d(on) (ms) t a = 125c t a = 25c t a = ?45c v in (v) 0 10 20 30 40 50 60 0 10 20 30 40 50 4367 g15 t d(on) (ms) v out v in gate dual si7942 1k, 10f load on v out 5ms/div 20v/div 1v/div 4367 g16 gnd gnd gate v out shdn 400s/div 3v/div gnd 5v/div 4367 g17 v in = 12v dual si7942 mosfet 100f , 12? load shdn gate v out dual si7942 mosfet 100f, 12? load v in = 12v 400s/div 5v/div gnd 3v/div 4367 g18 ltc4367 ac blocking turn-on timing turn-off timing downloaded from: http:///
lt c4367 7 4367fa for more information www.linear.com/ltc4367 pin functions exposed pad : the exposed pad may be left open or con - nected to device ground. fault : fault indication output . this high voltage open drain output is pulled low if uv is below its monitor threshold , if ov is above its monitor threshold , if shdn is low , or if v in has not risen above v in(uvlo) . gate: gate drive output for external n-channel mosfets . an internal charge pump provides 35a of pull-up current and up to 13.1v of enhancement to the gate of an external n-channel mosfet . when turned off , gate is pulled just below the lower of v in or v out . when v in goes negative , gate is automatically connected to v in . gnd: device ground. ov: overvoltage comparator input . connect this pin to an external resistive divider to set the desired v in overvoltage fault threshold . this input connects to an accurate , fast (1s) comparator with a 0.5v rising threshold and 25mv of hysteresis . when ov rises above its threshold , a 60ma current sink pulls down on the gate output . when ov falls back below 0.475v, and after a 32ms gate turn-on delay waiting period (500s for ltc4367-1), the gate charge pump is enabled . the low leakage current of the ov input allows the use of large valued resistors for the external resistive divider . connect to gnd if unused . if the voltage at the ov pin can rise above 5v, place a low leakage zener clamp on the ov pin. shdn : shutdown control input . shdn high enables the gate charge pump which in turn enhances the gate of an external n-channel mosfet . a low on shdn generates a pull down on the gate output with a 90 a current sink and places the ltc4367 in low current mode (5a ). if unused , connect to v in with a 510k resistor . if v in goes above 80v, the shdn pin voltage must be kept below 80v (see applications information).uv : undervoltage comparator input . connect this pin to an external resistive divider to set the desired v in undervolt - age fault threshold . this input connects to an accurate , fast (1s) comparator with a 0.5v falling threshold and 25mv of hysteresis . when uv falls below its threshold , a 60ma current sink pulls down on the gate output . when uv rises back above 0.525v, and after a 32ms gate turn- on delay waiting period (500s for ltc4367-1), the gate charge pump is enabled . the low leakage current of the uv input allows the use of large valued resistors for the external resistive divider . if unused and v in is less than 80v, connect to v in with a 510k resistor. v in : power supply input . maximum protection range : C40v to 100v. operating range: 2.5v to 60v.v out : output voltage sense input . this pin senses the volt - age at the output side of the external n-channel mosfet . the gate charge pump voltage is referenced to v out . it is used as the charge pump input when v out is greater than approximately 5v. downloaded from: http:///
lt c4367 8 4367fa for more information www.linear.com/ltc4367 block diagram v in C40v to 100v 5v internalsupply 5v internal supply ldo 2.2v uvlo 0.5v 0.5v gnd 25mv hysteresis 4367 bd i gate 35a reverse protection closes switch when v in is negative enable gate pulldown fault off turn off 60ma 90a shdn shdn gate charge pump f = 400khz v out uvov ? + delay timers logic ? + ? + fault gate downloaded from: http:///
lt c4367 9 4367fa for more information www.linear.com/ltc4367 operation many of today s electronic systems get their power from external sources such as ac or wall adaptors , batteries and custom power supplies . figure ? 1 shows a supply ar - rangement using a dc barrel connector . power is supplied by an ac adaptor or , if the plug is withdrawn , by a remov - able battery . note that the polarity of the ac adaptor and barrel connector varies by manufacturer . trouble arises when any of the following occurs:? the batter y is installed backwards ? an ac adaptor of opposite polarity is attached ? an ac adaptor of excessive voltage is attached ? the battery is discharged below a safe level this can lead to supply voltages that are too high , too low, or even negative . if these power sources are applied directly to the electronic systems , the systems could be subject to damage . the ltc4367 is an input voltage fault protection n-channel mosfet controller . the part isolates an input supply from its load to protect the load from figure?1. polarity protection for dc barrel connectors unexpected supply voltage conditions , while providing a low loss path for qualified power.in the past , to protect electronic systems from improperly connected power supplies , system designers often added discrete diodes , transistors and high voltage comparators . the high voltage comparators enable system power only if the input supply falls within a desired voltage window . a schottky diode or p-channel mosfet typically added in series with the supply protects against reverse supply connections. the ltc4367 provides accurate overvoltage and undervolt - age comparators to ensure that power is applied to the system only if the input supply meets the user selectable voltage window . reverse supply protection circuits au - tomatically isolate the load from negative input voltages . during normal operation , a high voltage charge pump enhances the gate of external n-channel power mosfets . power consumption is 5a during shutdown and 70a while operating . the ltc4367 integrates all these func - tions in 8-lead msop and 3mm 3mm dfn packages. v in uvov shdn 2.5v to 60voperating range 4367 f01 v out fault gate gnd ltc4367 r3 C40v to 100v protection range ac adaptor input ov, uv protection thresholds set to satisfy load circuit r2r1 r4 m1 m2 load circuit + C battery downloaded from: http:///
lt c4367 10 4367fa for more information www.linear.com/ltc4367 v out (v) 0 0 ?v gate (v) 2 4 6 10 8 1412 15 4367 f03 10 5 t a = 25c i gate = ?1a v in = 60v v in = 12v v in = 5v v in = 2.5v v in = 3.3v applications information the ltc4367 is an n-channel mosfet controller that protects a load from faulty supply connections . a basic application circuit using the ltc4367 is shown in figure ?2 the circuit provides a low loss connection from v in to v out as long as the voltage at v in is between 3.5v and 18v. voltages at v in outside of the 3.5v to 18v range are prevented from getting to the load and can be as high as 100v and as low as C40v. the circuit of figure ? 2 protects against negative voltages at v in as shown . no other external components are needed.during normal operation , the ltc4367 provides up to 13.1v of gate enhancement to the external back-to-back n-channel mosfets . this turns on the mosfets , thus connecting the load at v out to the supply at v in . gate drive the ltc4367 turns on the external n-channel mosfets by driving the gate pin above v out . the voltage difference between the gate and v out pins ( gate drive ) is a function of v in and v out . figure? 3 highlights the dependence of the gate drive on v in and v out . when system power is first turned on ( shdn low to high , v out = 0v), gate drive is at a maximum for all values of v in . this helps prevent start-up problems into heavy loads by ensuring that there is enough gate drive to support the load. as v out ramps up from 0v, the absolute value of the gate voltage remains fixed until v out is greater than the lower of (v in C 1v) or 5v. once v out crosses this threshold , gate drive begins to increase up to a maximum of 13.1v ( for v in 12v). the curves of figure ? 3 were taken with a gate load of C1a. if there were no load on gate , the gate drive for each v in would be slightly higher. note that when v in is at the lower end of the operating range, the external n-channel mosfet must be selected with a corresponding lower threshold voltage. figure?2. ltc4367 protects load from C40v to 100v v in faults figure?3. gate drive (gate C v out ) vs v out v in uvov shdn ov = 18vuv = 3.5v 4367 f02 v out fault gate v in 12v nominal v out 3.5v to 18v si7942 100v dual gnd ltc4367 r4453k c out 100f r31370k r2 243k r1 59k + m1 m2 downloaded from: http:///
lt c4367 11 4367fa for more information www.linear.com/ltc4367 overvoltage and undervoltage protection the ltc4367 provides two accurate comparators to moni - tor for overvoltage (ov) and undervoltage (uv) conditions at v in . if the input supply rises above the user adjustable ov threshold , the gate of the external mosfet is quickly turned off , thus disconnecting the load from the input . similarly, if the input supply falls below the user adjust - able uv threshold , the gate of the external mosfet also is quickly turned off . figure ? 4 shows a uv / ov application for an input supply of 12v.the external resistive divider allows the user to select an input supply range that is compatible with the load at v out . furthermore , the uv and ov inputs have very low leakage currents (typically < 1na at 100 c), allowing for large values in the external resistive divider . in the applica - tion of figure ?4, the load is connected to the supply only if v in lies between 3.5v and 18v. in the event that v in goes above 18v or below 3. 5v , the gate of the external n-channel mosfet is immediately discharged with a 60ma current sink, thus isolating the load from the supply. applications information v in 12v uv = 3.5v ov = 18v 4367 f04 discharge gatewith 60ma sink ltc4367 ov comparator uv comparator r31820k uv 0.5v0.5v ov r2243k r159k ? + 25mv ? + 25mv figure?4. uv, ov comparators monitor 12v supply table 1 lists some external mosfets compatible with different v in supply voltages. table 1. dual mosfets for various supply ranges v in mosfet v th(max) v gs(max) v ds(max) r ds(on) () 2.5v sia920 0.7v 5v 8v 0.027 3.3v sia910 1.0v 8v 12v 0.028 3.3v si6926 1.0v 8v 20v 0.030 5v sia906 1.4v 12v 20v 0.046 5v si9926 1.5v 12v 20v 0.018 >12v siz340 2.4v 20v 30v 0.010 >12v si4288 2.5v 20v 40v 0.020 >12v si7220 3v 20v 60v 0.060 >12v si4946 3v 20v 60v 0.040 >12v fds3890 4v 20v 80v 0.044 >12v si7942 4v 20v 100v 0.049 >12v fds3992 4v 20v 100v 0.054 >12v si7956 4v 20v 150v 0.105 downloaded from: http:///
lt c4367 12 4367fa for more information www.linear.com/ltc4367 figure? 5 shows the timing associated with the uv pin . once a uv fault propagates through the uv comparator (t fault ), the fault output is asserted low and a 60ma current sink discharges the gate pin . as v out falls , the gate pin tracks v out . applications information figure? 6 shows the timing associated with the ov pin . once an ov fault propagates through the ov comparator (t fault ), the fault output is asserted low and a 60ma current sink discharges the gate pin . as v out falls , the gate pin tracks v out . procedure for selecting uv / ov external resistor values the following 3- step procedure helps select the resistor values for the resistive divider of figure ?4. this procedure minimizes uv and ov offset errors caused by leakage currents at the respective pins. 1. choose maximum tolerable offset error at the uv pin , v os(uv) . divide by the worst case leakage current at the uv pin , i leak ( 10na). set the sum of r1 + r2 equal to v os(uv) divided by 10na. note that due to the presence of r3, the actual offset at uv will be slightly lower: r1 + r2 v os(uv) i leak 2. select the desired v in uv trip threshold , uv th . find the value of r3: r3 = v os(uv) i leak ? uv th C 0.5v 0.5v ?? ? ?? ? 3. select the desired v in ov trip threshold , ov th . find the values of r1 and r2: r 1 = v os(uv) i leak ?? ? ?? ? + r3 ov th ? 0.5v r 2 = v os(uv) i leak C r 1 the example of figure ? 4 uses standard 1 % resistor values . the following parameters were selected: v os(uv) = 3mv i leak = 10na uv th = 3.5v ov th = 18v 4367 f05 fault gate t fault t gate(fast) v uv v uv + v uvhyst t d(on) external n-channel mosfets turn off uv 4367 f06 t fault t gate(fast) v ov v ov C v ovhyst t d(on) external n-channel mosfet turns off ov fault gate figure?5. uv timing (ov < (v ov C v ovhyst ), shdn > 1.2v) figure?6. ov timing (uv > (v uv + v uvhyst ), shdn > 1.2v) when both the uv and ov faults are removed , the ex - ternal mosfet is not immediately turned on . the input supply must remain within the user selected power good window for at least 32ms (t d(on) ) before the load is again connected to the supply . this gate turn-on delay period filters noise ( including line noise ) at the input supply and prevents chattering of power at the load . for applications that require faster turn-on after a fault , the ltc4367-1 provides a 500s gate turn-on delay. downloaded from: http:///
lt c4367 13 4367fa for more information www.linear.com/ltc4367 applications information the resistor values can then be solved: 1. r1 + r2 = 3mv 10na = 300k 2. r3 = 3mv 10na ? 3.5v C 0.5v ( ) 0.5v = 1.8m the closest 1% value: r3 = 1.82m: 3. r1 = 300k + 1.82m 2 ? 18v = 58.9k the closest 1% value: r1 = 59k: r2 = 300k C 59k = 241k the closest 1% value: r2 = 243k therefore: ov = 17.93v, uv = 3.51v. reverse v in protection the ltc4367 s rugged and hot-swappable v in input helps protect the more sensitive circuits at the output load . if the input supply is plugged in backwards , or a negative supply is inadvertently connected , the ltc4367 prevents this negative voltage from passing to the output load. the ltc4367 employs a novel , high speed reverse supply voltage monitor . when the negative v in voltage is detected , an internal switch connects the gates of the external back- to-back n-channel mosfets to the negative input supply . as shown in figure ?7, external back-to-back n-channel mosfets are required for reverse supply protection . when v in goes negative , the reverse v in comparator closes the internal switch , which in turn connects the gates of the external mosfets to the negative v in voltage . the body diode (d1) of m1 turns on , but the body diode (d2) of m2 remains in reverse blocking mode . this means that the common source connection of m1 and m2 remains about a diode drop higher than v in . since the gate voltage of m2 is shorted to v in , m2 will be turned off and no cur - rent can flow from v in to the load at v out . note that the voltage rating of m2 must withstand the reverse voltage excursion at v in . figure? 8 illustrates the waveforms that result when v in is hot plugged to C20v. v in , gate and v out start out at ground just before the connection is made . due to the parasitic inductance of the v in and gate connections , the voltage at the v in and gate pins ring significantly below C20v. therefore , a 40v n-channel mosfet was selected to survive the overshoot. the speed of the ltc4367 reverse protection circuits is evident by how closely the gate pin follows v in during the negative transients . the two waveforms are almost indistinguishable on the scale shown. the trace at v out , on the other hand , does not respond to the negative voltage at v in , demonstrating the desired reverse supply protection . the waveforms of figure ? 8 were captured using a 40v dual n-channel mosfet , a 10f ceramic output capacitor and no load current on v out . figure?7. reverse v in protection circuits figure?8. hot swapping v in to C20v v out v in gate C20v 400ns/div 5v/div 4367 f08 gnd v in 4367 f07 v out gate v in = C40v reverse v in comparator closes switch when v in is negative gnd ltc4367 m1 d1 d2 m2 + ? + to load c out downloaded from: http:///
lt c4367 14 4367fa for more information www.linear.com/ltc4367 gate turn-on delay timer the ltc4367 has a gate turn-on delay timer that filters noise at v in and helps prevent chatter at v out . after either an ov or uv fault has occurred , the input supply must return to the desired operating voltage window for at least 32ms (t d(on) ) in order to turn the external mosfet back on as illustrated in figure ? 5 and figure ?6. for applications that require faster turn-on after a fault , the ltc4367-1 provides a 500s gate turn-on delay. going out of and then back into fault in less than t d(on) will keep the mosfet off continuously . similarly , coming out of shutdown ( shdn low to high ) triggers an 800s start-up delay timer (see figure?11). the gate turn-on delay timer is also active while the part is powering up . the timer starts once v in rises above v in(uvlo) and v in lies within the user selectable uv /ov power good window. see figure?9. shutdownthe shdn input turns off the external mosfets in a controlled manner . when shdn is asserted low , a 90a current sink slowly begins to turn off the external mosfets . once the voltage at the gate pin falls below the voltage at the v out pin , the current sink is throttled back and a feedback loop takes over . this loop forces the gate voltage to track v out , thus keeping the external mosfets off as v out decays . note that when v out < 2.2v, the gate pin is pulled to within 400mv of ground. weak gate turn off reduces load current slew rates and mitigates voltage spikes due to parasitic inductances . to further decrease gate pin slew rate , place a capacitor across the gate and source terminals of the external mos - fets. the waveforms of figure ? 10 were captured using the s i7942 dual n-channel mosfets , and a 2a load with 100f output capacitor. applications information 4367 f09 gate mosfet off mosfet on v in v in(uvlo) t d(on) figure?9. gate turn-on delay timing during power-on (ov = gnd, uv = shdn = v in ) figure?10. shutdown: gate tracks v out as v out decays gate v out t gate(slow) gate = v out t start t shdn(f) ? v gate shdn 4367 f11 fault figure?11. shutdown timing fault status the fault high voltage open drain output is driven low if shdn is asserted low , if v in is outside the desired uv /ov voltage window , or if v in has not risen above v in(uvlo) . figure?5, figure ? 6 and figure ? 11 show the fault output timing. shdn gate v out 100f, 6? load on v out dual si7942 mosfet v in = 12v 400s/div 5v/div 4367 f10 gnd select between two input supplies with the part in shutdown, the v in and v out pins can be driven by separate power supplies . the ltc4367 then automatically drives the gate pin just below the lower of downloaded from: http:///
lt c4367 15 4367fa for more information www.linear.com/ltc4367 the two supplies , thus turning off the external back-to-back mosfets . the application of figure ? 12 uses two ltc4367 s to select between two power supplies . care should be taken to ensure that only one of the two ltc4367 s is enabled at any given time. applications information figure?12. selecting one of two supplies v in v2 shdn 4367 f12 v out gate ltc4367 v in v1 sel 01 out v1v2 out m2 m1 m2 m1 sel shdn v out gate ltc4367 limiting inrush current during turn-on the ltc4367 turns on the external n-channel mosfet with a 35a current source . the maximum slew rate at the gate pin can be reduced by adding a capacitor on the gate pin: slew rate = 35a c gate since the mosfet acts like a source follower , the slew rate at v out equals the slew rate at gate. therefore, inrush current is given by: i inrush = c out c gate ? 35a for example , a 1a inrush current to a 330f output capacitance requires a gate capacitance of: c gate = 35a ? c out i inrush c gate = 35a ? 330f 1a = 11.6nf the 12nf c gate capacitor in the application circuit of figure? 14 limits the inrush current to just under 1a. r gate makes sure that c gate does not affect the fast gate turn off characteristics during uv / ov faults , or during reverse v in connection . r5 a and r5 b help prevent high frequency oscillations with the external n-channel mosfet and related board parasitics. figure?13. single mosfet application protects against 100v figure?14. limiting inrush current with c gate single mosfet applicationwhen reverse v in protection is not needed , a single external n-channel mosfet may be used . the application circuit of figure ? 13 connects the load to v in when v in is less than 30v , and uses the minimal set of external components . v in uvov shdn ov = 30v 4367 f13 v out fault gate v in 24v sir870 100v v out gnd ltc4367 r21870k r1 40.2k c out 100f + r4499k 4367 f14 v in v in v out r5b 10 r5a 10 c out 330f v out gate ltc4367 r gate 5.1k c gate 12nf + m2 m1 downloaded from: http:///
lt c4367 16 4367fa for more information www.linear.com/ltc4367 applications information transients during ov fault the circuit of figure ? 15 is used to display transients dur - ing an overvoltage condition . the nominal input supply is 48v and it has an overvoltage threshold of 60v. the parasitic inductance is that of a 1 foot wire ( roughly 300nh). figure? 16 shows the waveforms during an overvoltage condition at v in . these transients depend on the parasitic inductance and resistance of the wire along with the ca - pacitance at the v in node . d1 is an optional power clamp ( tvs , transzorb ) recommended for applications where v in can ring above 100v. no clamp was used to capture the waveforms of figure ?16. in order to maintain reverse supply protection , d1 must be a bidirectional clamp rated for at least 225w peak pulse power dissipation. 400ns/div v in 20v/div v out 20v/div gate i in 2a/div 4367 f16 60v 60v0a figure?15. ov fault with large v in inductance figure?16. transients during ov fault when no transzorb ( tvs ) is used v in uvov shdn ov = 60v 4367 f15 v out fault gate m1 m2 v in 48v si7942 100v dual 12 inch wire length v out gnd ltc4367 r22430k r120.5k r4523k c out 100f + c in 1000f d1optional + 22 downloaded from: http:///
lt c4367 17 4367fa for more information www.linear.com/ltc4367 regulator applications hysteretic regulator built-in hysteresis and the availability of both inverting and noninverting control inputs ( ov and uv ) facilitate the design of hysteretic regulators . figure ? 17 shows how the ltc4367 -1 can protect a load from ov transients , while regulating the output voltage at a user-defined level . when the output voltage reaches its ov limit , the ltc4367-1 turns off the external mosfets . the load current then discharges the output capacitance until ov falls below the hysteresis voltage . the external mosfets are turned back on after a 500s delay . figure ? 18 shows the waveforms for the circuit of figure ?17. the voltage spikes on v in result from the parasitic inductance of the v in connector . see transient during 0v fault section for more details. solar charger figure? 19 shows a series regulator for a solar charger . the ltc4367 -1 connects the solar charger to the battery when the battery voltage falls below 13.9v ( after a 500s delay). conversely , when the battery reaches 14.6v, the ltc4367-1 immediately (2s) opens the charging path. regulation of the battery voltage is achieved by connect - ing a resistive divider from the battery to the accurate ov comparator input ( with 5 % hysteresis ). the fast rising response of the ov comparator prevents the battery voltage from rising above the user-selected threshold. applications information figure?17. hysteretic regulation of v out during ov transients figure?18. v out regulates at 16v when v in rises above desired level gnd v in v out 1ms/div 5v/div 4367 f18 v in 4367 f19 v out gate uv shdn 1/2 of si4214 1/2 of si4214 gnd ltc4367-1 ov m1 d1 d4 b130 d2 m2 + to load c batt 100f c byp 100nf 15wsolar panel r23.24m r1115k 14.6v off 13.9v on c ov 220pf 12v, 8ahgelcell figure?19. series hysteretic solar charger with reverse-battery and solar panel protection v in uv ov shdn 4367 f17 v out fault gate v in si4946 dual optional snubber v out gnd ltc4367-1 r4510k c load 47f c ov 220pf + r load 100 r21820k r159k 1f r71 downloaded from: http:///
lt c4367 18 4367fa for more information www.linear.com/ltc4367 applications information note that during initial start-up , the ltc4367 -1 will not turn on the external mosfets until a battery is first con- nected to the v in pin . to begin operation , v in must initially rise above the 2.2v uvlo lockout voltage . connecting the battery ensures that the ltc4367 -1 comes out of uvlo . 12v application with 150v transient protection figure? 20 shows a 12v application that withstands input supply transients up to 150v. when the input voltage ex - ceeds 17.9v, the ov resistive divider turns off the external mosfets. as v in rises to 150v, the gate of transistor m1 remains in the off condition , thus preventing conduction from v in to v out . note that m1 must have an operating range above 150v. resistor r6 and diode d3 clamp the ltc4367 supply volt - age to 50v. to prevent r6 from interfering with reverse operation, the recommended value is 1k or less . note that the power handling capability of r6 must be considered in order to avoid overheating during transients . d3 is shown as a bidirectional clamp in order to achieve reverse-polarity protection at v in . m2 is also required in order to protect v out from negative voltages at v in and should have an operating range beyond the breakdown of d3. if reverse protection is not desired remove m2 and connect the source of m1 directly to v out . mosfet selection to protect against a negative voltage at v in , the external n-channel mosfets must be configured in a back-to- back arrangement . dual n-channel packages are thus the best choice . the mosfet is selected based on its powe r handling capability , drain and gate breakdown voltages , and threshold voltage. the drain to source breakdown voltage must be higher than the maximum voltage expected between v in and v out . note that if an application generates high energy transients during normal operation or during hot swap , the external mosfet must be able to withstand this transient voltage . due to the high impedance nature of the charge pump that drives the gate pin , the total leakage on the gate pin must be kept low . the gate drive curves of figure 3 were measured with a 1a load on the gate pin . therefore , the leakage on the gate pin must be no greater than 1a in order to match the curves of figure ?3. higher leakage currents will result in lower gate drive . the dual n-channel mosfets shown in table 1 all have a maximum gate leakage current of 100na. additionally , table 1 lists representative mosfets that would work at different values of v in . layout considerations the trace length between the v in pin and the drain of the external mosfet should be minimized , as well as the trace length between the gate pin of the ltc4367 and the gates of the external mosfets. place the bypass capacitors at v out as close as possible to the external mosfet . use high frequency ceramic capacitors in addition to bulk capacitors to mitigate hot swap ringing . place the high frequency capacitors closest to the mosfet . note that bulk capacitors mitigate ringing by virtue of their esr . ceramic capacitors have low esr and can thus ring near their resonant frequency. figure?20. 12v application protected from 150v transients v in uvov shdn d3: smaj43ca bi-directional ov = 17.9v 4367 f20 v out fault gate v in 12v m1 fdd2572 m2 fds5680 v out gnd ltc4367 r4510k d3 r22050k r159k r61k downloaded from: http:///
lt c4367 19 4367fa for more information www.linear.com/ltc4367 package description please refer to http:// www .linear.com/product/ltc4367#packaging for the most recent package drawings. msop (ms8) 0213 rev g 0.53 0.152 (.021 .006) seating plane note:1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 C 0.38 (.009 C .015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 C 6 typ detail a detail a gauge plane 1 2 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.10 (.201) min 3.20 C 3.45 (.126 C .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc ms8 package 8-lead plastic msop (reference ltc dwg # 05-08-1660 rev g) downloaded from: http:///
lt c4367 20 4367fa for more information www.linear.com/ltc4367 package description please refer to http:// www .linear.com/product/ltc4367#packaging for the most recent package drawings. 3.00 0.10 (4 sides) note:1. drawing to be made a jedec package outline m0-229 variation of (weed-1) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 1 4 8 5 pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (dd8) dfn 0509 rev c 0.25 0.05 2.38 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 (2 sides) 2.10 0.05 0.50bsc 0.70 0.05 3.5 0.05 packageoutline 0.25 0.05 0.50 bsc dd package 8-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1698 rev c) downloaded from: http:///
lt c4367 21 4367fa for more information www.linear.com/ltc4367 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use . linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . revision history rev date description page number a 03/16 updated typical application and figures 1, 2, 13, 15 updated shdn , uv input current rating changed i shdn test condition to 10v from 0.75v updated graphs g09 and g12updated shdn and uv pin functions 1, 9, 10, 15, 16 24 5, 6 7 downloaded from: http:///
lt c4367 22 4367fa for more information www.linear.com/ltc4367 ? linear technology corporation 2015 lt 0316 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4367 related parts typical application ltc4367 protects step down regulator from C30v to 30v v in faults part number description comments ltc4365 overvoltage, undervoltage and reverse supply protection controller wide operating range: 2.5v to 34v, protection range: C40v to 60v, no tvs required for most applications lt4363 surge stopper overvoltage/overcurrent protection regulator wide operating range: 4v to 80v, reverse protection to C60v, adjustable output clamp voltage ltc4364 surge stopper with ideal diode 4v to 80v operation, C40v reverse input, C20v reverse output ltc4366 floating surge stopper 9v to >500v operation, 8-pin tsot and 3mm 2mm dfn packages ltc4361 over voltage/overcurrent protection controllers 5.8v overvoltage threshold, 85v absolute maximum ltc2909 triple/dual inputs uv/ov negative monitor pin selectable input polarity allows negative and ov monitoring ltc2912/ltc2913 single/dual uv/ov voltage monitor adjustable uv and ov trip values, 1.5% threshold accuracy ltc2914 quad uv/ov monitor for positive and negative supplies ltc2955 pushbutton on/off controller automatic turn-on, 1.5v to 36v input, 36v pb input lt4256 positive 48v hot swap controller with open-circuit detect foldback current limiting, open-circuit and overcurrent fault output, up to 80v supply ltc4260 positive high v oltage hot swap controller with adc and i 2 c wide operating range 8.5v to 80v ltc4352 ideal mosfet oring diode external n-channel mosfets replace oring diodes, 0v to 18v ltc4354 negative voltage diode-or controller controls two n-channel mosfets, 1.2s turn-off, C80v operation ltc4355 positive voltage diode-or controller controls two n-channel mosfets, 0.4s turn-off, 80v operation lt1913 step-down switching regulator 3.6v to 25v input, 3.5a maximum current, 200khz to 2.4mhz v in uvov shdn ov = 18vuv = 3.5v 4367 ta02 v out fault gate si4214 30v dual n-channel v out protected from C30v to 30v v in 12v nominal v out gnd ltc4367 510k 10f 1820k243k 59k sw fb v c pg rt v in bd output5v 3.5a 0.47f 47f 100k 15k 63.4k 4.7h 536k gnd lt1913 run/ss boost sync 680pf downloaded from: http:///

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